With reference to FIG. 1, a semiconductor structure 10 includes a substrate 12 having formed therein a well 14, which is a region of the substrate 12 that is doped oppositely to the doping of the substrate 12. For example, the substrate 12 of FIG. 1 is a p-type substrate. A deep n-type well 16 is implanted into the substrate 12 to form a buried layer. A surface n-well in areas 18, 20 surrounds the buried layer n-type well 16 to form a doughnut shape where the center is a p-type well 14 that is now completely isolated from the substrate 12, thus allowing a separate bias voltage. Various semiconductor devices can be fabricated into the well 14, such as an n-channel transistor 22. In practice, a large number of semiconductor devices can be fabricated into the well 14 to form an integrated circuit.
The junction between the well 14 and the deep n-well 16 forms a p-n junction or diode 24 that is schematically illustrated in phantom in FIG. 1. A similar diode 26 is formed by a p–n junction between the deep n-well 16 and the p-type substrate 12. The diodes 24, 26 are inherently formed with a back-to-back connection, thereby isolating the p-well 14 from the substrate 12, and, therefore, from other devices that are also fabricated into the substrate 12. The p-well 14 is often biased to a negative bias voltage, which is often provided by a negative voltage charge pump, commonly known as a Vbb charge pump. By fabricating the memory cell arrays in respective wells, each of several array wells can be isolated from each other and from other circuitry fabricated in the substrate 12. Similar diodes (not shown) are formed by the p–n junctions between the n-wells 18, 20 and both the p-well 14 and the substrate 12. However, the diodes are inherently coupled to each other back-to-back to isolate the p-well from the substrate 12. In practice, the n-wells 18, 20 are typically biased to a relatively large positive voltage, such as a supply voltage VCC or a positive pumped voltage VCCP, to maintain the diodes reverse or back-bias.
As explained above, fabricating integrated circuits into the wells also allows the wells 14 to be biased to a voltage that enhances the performance of integrated circuits fabricated in the wells 14. For example, it is common to bias the wells 14 in which DRAM arrays have been fabricated to a negative voltage, which reduces the leakage of access transistors (not shown) coupled to respective DRAM memory cells. As is well known in the art, reducing access transistor leakage allows the memory cells to store data for a longer period to reduce refresh rates. However, it is desirable to perform post-fabrication testing of the integrated circuit under “worst case” conditions for the purpose of detecting failures that are likely to occur after the integrated circuit is placed in service. Again using the example of DRAM arrays, it is desirable to test the data retention time of a DRAM array fabricated in the well 14 with the well 14 biased to ground voltage. If the data retention time is achieved with the well 14 biased to ground or a less negative voltage, then it will inherently do so when the well 14 is biased to a more negative voltage during operation. The test voltage can be applied to the well 14 from an externally accessible terminal 30. To allow the terminal 30 to be used for other purposes during use of an integrated circuit fabricated in the substrate 12, the terminal 30 is preferably coupled to the well 14 through a transistor 34 fabricated into the substrate 12.
FIG. 2 shows a semiconductor structure 40 in which a p-type well or core 42 is fabricated in a substrate 44, and a DRAM array is 46 fabricated in the p-type core 42. Like the p-well 14 of FIG. 1, the core 42 is isolated from the substrate 12 by n-wells 18, 20 (not shown in FIG. 2) and the deep n-well 16. The core 42 is coupled through a p+region 47 to an externally accessible terminal 48 through an n-channel transistor 50. The transistor 50 is fabricated in a p-type well 52 in which first and second n-type source-drain regions 56, 58 are fabricated. The p-well 52 is also isolated from the substrate 12 by n-wells 18, 20 and the deep n-well 16. A gate electrode 60 is fabricated between the source-drain regions 56, 58 and is insulated from the well 42 by a gate insulating layer 62 to form an MOS device. The externally accessible terminal 48 is connected to the first source-drain region 56 The second source-drain region 58 is connected to the well 52 through a p+ region 54 that is more positively doped than the doping of the p-well 52 and to the core 42 in which the array 46 is fabricated through a similar p+ region 55. As is well-known in the art, coupling the terminal 48 to the well 52 and to the core 42 through p+ regions 54, 55, respectively, reduces the resistance of the contact with the well 52 and to the core 42. As explained above with reference to FIG. 1, the junction between each p-type region and each n-type region forms a diode, one of which 68 is shown in phantom in FIG. 2. The significance of this diode 68 will be explained with reference to FIG. 3. There is also a diode created by the junction between the n-type source-drain region 58 and the p-type well 52, but since this diode would be shorted out by the direct connection between the region 58 and well 52, it is not shown in FIG. 2.
In operation, the transistor 50 isolates the externally accessible terminal 48 from the core 42 during normal use of an integrated circuit, such as a DRAM device, fabricated in the substrate 44. During this time, the core 42 can be biased to a negative voltage while the substrate 44 remains at ground potential. When the array 46 is to be tested under “worst-case” conditions, a positive voltage is applied to the gate electrode 60 by suitable means to form a conductive n-type channel between the source-drain regions 56, 58. The transistor 50 then couples the externally accessible terminal 48 to the core 42 so that a positive test voltage can be applied to the core 42 through the terminal 48. A negative test voltage can also be applied to the core 42 through the terminal 48 when the transistor 50 is turned ON. However, if the negative test voltage is more than about 0.6 v less than the voltage to which the core 42 is biased by a Vbb charge pump (not shown in FIG. 2), the diode 68 will be forward biased. As a result, the core 42 will be coupled to the externally accessible terminal 48 regardless of the conductive state of the transistor 50.
The problem caused by the diode 68 becoming forward-biased by a negative test voltage will now be explained with reference to FIG. 3. FIG. 3 shows a portion of a DRAM device 70 having two DRAM cores 72, 74 coupled to respective Vbb charge pumps 76, 78. The cores 72, 74 are also coupled to an externally accessible terminal 80 by respective transistors 82, 84, each of which is controlled by a respective select signal, Sel. A and Sel. B, respectively. The diodes 68 coupled between the source-drain regions 56, 58 (FIG. 2) of the transistors 82, 84 are also shown in FIG. 3. Although the DRAM device 70 is shown in FIG. 3 as having two DRAM cores 72, 74, it will be understood that other DRAM devices can have a large number of DRAM cores.
During testing of the DRAM device 70, it is desirable to individually test the operation of each of the cores 72, 74 without affecting the operation of the core not being tested. For example, it is desirable to be able to apply a negative or positive test voltage to the terminal 80, and then individually turn ON each of the transistors 82, 84 to couple the test voltages to the respective cores 72, 74. However, when a test voltage is applied to the terminal 80 that is significantly more negative than the bias voltages being supplied to the cores 72, 74 by the Vbb charge pumps 76, 78, the OFF transistor 82, 84 will effectively be rendered conductive by the diode 68 becoming forward-biased. For example, when the Sel. B signal is driven high to turn ON the transistor 84, a large negative test voltage can be applied to the core 74 from the terminal 80. However, this test voltage will also be applied to the core 72 through the diode 68 formed in parallel with the transistor 82. For this reason, it is not possible to adequately test the cores of an integrated circuit using the circuitry shown in FIG. 2, since a large negative voltage cannot be applied to the individual cores. There is therefore a need for a circuit and method that would allow integrated circuit cores to be individually tested with relatively large negative and positive test voltages.